- Data buffering
Due to the low speed of I/O devices and the high speed of CPU and memory, a buffer must be set up in the controller. When outputting, use this buffer to temporarily store data transmitted from the host at high speed, and then transfer the data in the buffer to the I/O device at the rate that the I/O device has; During input, the buffer is used to temporarily store data sent from the I/O device. After receiving a batch of data, the data in the buffer is quickly transmitted to the host.
- Error control
The device controller also manages error detection of data transmitted by I/O devices. If an error is found during transmission, the error detection code is usually set and reported to the CPU. The CPU then cancels the data transmitted this time and performs a new transmission. This ensures the accuracy of data input.
- Data exchange
This refers to the implementation of data exchange between CPUs and controllers, as well as between controllers and devices. For the former, data is written to the controller in parallel by the CPU through the data bus, or read from the controller in parallel; For the latter, the device inputs data into the controller or transmits data from the controller to the device. For this purpose, data registers must be set up in the controller.
- Status description
The status controller for identifying and reporting equipment should record the status of the equipment for the CPU to understand. For example, the CPU can only start the controller to read data from the device when it is in the ready to send state. For this purpose, a status register should be set up in the controller, where each bit reflects a certain state of the device. After the CPU reads the contents of the register, it can understand the status of the device.
- Receive and identify commands
The CPU can send various commands to the controller, and the device controller should be able to receive and recognize these commands. For this purpose, the controller should have corresponding control registers to store received commands and parameters, and decode the received commands. For example, a disk controller can receive 15 different commands such as Read, Write, Format, etc. sent by the CPU, and some commands also have parameters; Correspondingly, there are multiple registers and command decoders in the disk controller.
- Address recognition
Just as every unit in memory has an address, every device in the system also has an address, and the device controller must be able to recognize the address of each device it controls. In addition, in order for the CPU to write (or read) data to (or from) registers, these registers should have unique addresses.
